Exemplary embodiments of the present invention relate to a self-refresh control circuit for distributing current consumption during a self-refresh operation in a semiconductor memory device, and a control method thereof.
Unlike Static Random Access Memory (SRAM) or flash memory, a Dynamic Random Access Memory (DRAM) device loses data stored in its memory cells over time. This is because a memory cell of a DRAM device typically includes a transistor and a capacitor, where charge for stored data in the capacitor is discharged over time. Thus, a refresh operation for refreshing data stored in memory cells at desired periods is performed to prevent data loss. In performing a refresh operation, during the retention time of each memory cell of a memory bank, a refresh operation is performed at least once by activating a word line into an active state and amplifying data. Herein, the retention time of a memory cell is a time that data of a memory cell can be maintained without a refresh operation after the initial data storage.
In performing a refresh operation, an auto-refresh mode and/or a self-refresh mode may be used. The auto-refresh mode is a mode where a refresh operation is performed by an applied command in a system including a DRAM device, and the self-refresh mode is a mode where a DRAM device performs the refresh operation by itself when a system is not operated for a certain time.
FIG. 1 is a block diagram of a conventional self-refresh control circuit, and FIG. 2 is a timing diagram of internal signals of the self-refresh control circuit shown in FIG. 1.
Referring to FIG. 1, the conventional self-refresh control circuit includes a counter 101, an active signal generator 103, and an address generator 105.
The counter 101 periodically generates a refresh pulse PSRF when a self-refresh signal SREF is activated. Herein, the self-refresh signal SREF is a signal activated to a logic high level in a self-refresh mode duration of a DRAM device. According to an example, the period when the refresh pulse PSRF is generated may be 7.8 μs.
The active signal generator 103 generates a bank active signal BKACT<0:7> for activating banks (not shown) of a core region into an active state, when the refresh pulse PSRF is applied. Here, according to an example, the core region includes 8 banks.
The address generator 105 generates a row address XADD to activate a word line of each bank, and when the refresh pulse PSRF is applied, the address generator 105 sequentially increases the row address XADD so as to activate all word lines in the bank sequentially.
However, as illustrated in FIG. 2, since the self-refresh operation simultaneously activates a plurality of banks each of which includes a plurality of memory cells, high-peak current is generated. When a system performs the refresh operation for each bank in the auto-refresh mode, peak current of a system may be controllable to some extent. In the self-refresh mode, however, where the refresh operation is performed by an internal oscillator, all DRAM devices in a module may simultaneously perform a refresh operation, where the amount of instant current consumption may be several times that of the auto-refresh mode. Since Double Data Rate Three Synchronous dynamic Random Access Memory (DDR3) devices and DDR4 devices are supplied with low external voltages, power consumption in the self-refresh operation may exceed that allowed under the applied external voltages and thus render the refresh operation to be unstable.